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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
2.5.16 Supply Voltage Terminal Functions
Table 2-21. Supply Voltage Terminal Functions
www.ti.com
SIGNAL
NAME
NO.
TYPE (1)
(2)
OTHER (3)
(4)
DESCRIPTION
SUPPLY VOLTAGES
F6
H8
1.05-V Digital Core supply voltage (60 or 75 MHz)
CV DD
J6
K10
PWR
1.3-V Digital Core supply voltage (100 or 120 MHz)
L5
F7
K7
DV DDIO
K12
N14
PWR
1.8-V, 2.5-V, 2.75-V, or 3.3-V I/O power supply for non-EMIF and non-RTC I/Os
The DV DDIO must always be powered for proper operation.
P3
P8
A2
A5
E6
F5
1.8-V, 2.5-V, 2.75-V, or 3.3-V EMIF I/O power supply
Note: When EMIF is not used, it is permissable to ground the DV DDEMIF supply pins
if the following conditions are all met:
? At least one DV DDEMIF package ball (A2, A5, E6, F5, G5, H5, H7, J5, P2) is
grounded. The others must be either floating or grounded.
DV DDEMIF
G5
PWR
?
All signal pins that use DV DDEMIF as their I/O supply voltage (i.e., all pins listed
H5
in Table 2-8 , External Memory Interface Terminal Functions), regardless of
multiplexing options, are either:
H7
J5
P2
–
–
–
all grounded
all floating (not driven by any external source), or
any combination of grounded or floating.
1.05-V thru 1.3-V RTC digital core and RTC oscillator power supply.
CV DDRTC
C8
PWR
Note: The CV DDRTC must always be powered by an external power source even
though RTC is not used. CV DDRTC cannot be powered by any of the on-chip LDOs.
1.8-V, 2.5-V, 2.75-V, or 3.3-V I/O power supply for RTC_CLOCKOUT and WAKEUP
pins.
DV DDRTC
F8
PWR
Note: The DV DDRTC can be tied to ground (V SS ) when the RTC_CLKOUT and
WAKEUP pins are not permanently used. In this case, the WAKEUP pin must be
configured as output by software (see Table 5-24 , RTCPMGT Register Bit
Descriptions ).
V DDA_PLL
C10
PWR
see
Section 4.2 ,
1.3-V Analog PLL power supply for the system clock generator (PLLOUT ≤ 120
MHz).
ROC
see
This signal can be powered from the ANA_LDOO pin.
3.3 V USB Analog PLL power supply.
USB_V DDPLL
G8
S
Section 4.2 ,
ROC
When the USB peripheral is not used, the USB_V DDPLL signal should be connected
to ground (V SS ).
see
1.3-V digital core power supply for USB PHY.
USB_V DD1P3
J13
S
Section 4.2 ,
ROC
When the USB peripheral is not used, the USB_V DD1P3 signal should be connected
to ground (V SS ).
(1)
(2)
(3)
(4)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-
supply current. Prevent this current by externally terminating it or enabling IPD/IPU, if applicable.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors .
Specifies the operating I/O supply voltage for each signal
44
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